Fabrikasi dan pencirian teknologi 0.13 um nMOS

Ahmad, Afandi (2003) Fabrikasi dan pencirian teknologi 0.13 um nMOS. Masters thesis, Universiti Kebangsaan Malaysia.

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Abstract

The objective of this project is to design and simulate an nMOS transistor with a channel size of o. I 3 )lm. Implementing the scaling law, nMOS transistor o. 13 )lm is designed from a CMOS transistor 0.18 )lm recipe that had been designed and simulated previously using the same method. Some important parameters such as channel size, gate oxide thickness, ion implanted for voltage threshold modification had to be adjusted in searching the project goals. Fabrication and simulation is done using Virtual Wafer Fabrication (VWF) software by Silvaco Inc. TCAD Tools. Two primary tools are used during this project, which are ATHENA and ATLAS. ATHENA works as a simulation tool for the device fabrication process and ATLAS for electrical characteristics simulation. The simulation results are given in two-dimensional display using TONYPLOT editor. From this study, the value of threshold voltage (VTH) for nMOS transistor is 0.23503 V, junction depth (X}) is O. 198707 )lm; and the value of polysilicon sheet resistance is 8.63937 ohm/square. As a conclusion, the objective of this project is achieved. The tools of ATHENA and ATLAS and the scaling factor (5) = 1.38 are relevant.

Item Type:Thesis (Masters)
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
ID Code:1121
Deposited By:Norfauzan Md Sarwin
Deposited On:19 Apr 2011 15:09
Last Modified:29 Apr 2011 14:43

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