A study on ultra-low power and large-scale design of digital circuit for wireless communications

Zainal, Shamian (2010) A study on ultra-low power and large-scale design of digital circuit for wireless communications. PhD thesis, Hokkaido University.

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Abstract

The continuous growth of recent mobile and portable devices has caused a push greater towards low-power circuit designs. Various methods and techniques have been found, for example, the utilization of concurrent or pipeline architecture with low supply voltage for traditional circuits. Proper designs of subthreshold circuits operating in a weak inversion region achieves ultra-low threshold and supply voltages and has been studied for both analog and digital circuits. The analog circuit has been studied and implemented in many areas such as speech signal and image processing. On the other hand, digital circuits have been studied for very low clock frequency and can be applied in medical devices such as pacemakers and defibrillators. For the idle state of low-power, subthreshold voltage condition has been used for microprocessors in ultra-low voltage operation and leakage current. The idea to study subthreshold operation comes after much research carried out through conventional analysis focusing on, for example, low power, low voltage, low frequency, and application in small circuit systems. Recently, as a result of the aggressive scaling of transistor size for high-performance applications, not only does subthreshold leakage current increase exponentially, but gate leakage and reverse-biased source-substrate and drain-substrate junction band-to-band tunneling (BTBT) currents also increase significantly. The tunneling currents are detrimental to the functionality of the devices. The well-known methods of low-power design (such as voltage scaling, switching activity reduction, architectural techniques of pipelining and parallelism, computer-aided design (CAD) techniques of device sizing, interconnect, and logic optimization). This may not be sufficient in many applications such as portable computing gadgets, and medical electronics, where ultra-low power consumption with medium frequency of operation is the primary requirement. To cope with this, several novel design techniques have been proposed. Energy recovery or adiabatic techniques are promising for reducing power in computation by orders of magnitude. However, they involve the use of high-quality inductors, which makes integration difficult. More recently, the design of digital subthreshold logic was investigated with transistors operated in the subthreshold region. The aim of this study is to achieve ultra-low power communication circuits operating at high frequency. In this situation, we focus on implementing large-scale subthreshold circuits and must explore a new design in which only the CMOS standard cell library is used and simplify the modeling procedure of subthreshold circuits. The conventional design involves subthreshold analysis on a transistor level or cell library preparation under multiple voltage conditions. This procedure has disadvantageous that requires a long time to estimate the circuit performance for operation in the subthreshold region. We proposed scale modeling so we need only to use a typical cell library, which is suitable for large-scale digital circuits such as wireless communication circuits. In the proposed method, each CMOS logic cell operating in the subthreshold region in circuit delays and power dissipation are analyzed and scaled factors are obtained by mapping from typical to subthreshold voltage conditions. This process does not need preparation of a special-purpose CMOS library operating in the sub-threshold region. The critical path delay is also obtained by scaling factors and used for determining the optimal voltage condition that satisfies the required timing constrains. For practical examples, we have designed wireless clrcuits of a channel equalizer, FIR filter and FlT used in an OFDM receiver. These circuits have been power dissipated by adjusting the overall voltage conditions to satisfy the required timing constrains of IEEE802.11a standard. Continuing from the first research, we explore the power reduction on dynamic wordlength and voltage scaling for digital signal processing circuits. The determination of wordlength in digital signal processing (DSP) affects system performance, hardware size, and power consumption. A large wordlength yields better performance in digital hardware but increases power consumption. A small wordlength degrades system performance if the dynamic range is insufficient. Use of a fixed wordlength determined in design-level lacks flexibility for such changeable environments. Use of a dynamic variable wordlength technique can maintain system performance and keep power consumption low by dynamically changing an optimal wordlength for various environments. This technique has been applied to an OFDM demodulator and to an equalizer. There are two ways in reducing power for variable wordlength. One is to decrease switching activities by stopping unnecessary bit operations. Variable wordlength chooses small and large wordlength modes. For a small wordlength mode, unused bits can be masked by zero values. Gated clocks are effective in halting switching activities for registers. However, it requires a clock management in its system. The other is voltage scaling (called as minimum power locus) to normalize a circuit delay for each wordlength mode. A small wordlength has a timing margin in a critical path when the timing delay of a large wordlength is adopted. It enables decreasing a voltage so as to have the same circuit delay of a large wordlength. Thus, dynamic wordlength and voltage scaling (DWVS) is suitable for power reduction in variable wordlength architecture. This second research focus is power modeling for DWVS. The work does transistor-level simulation or actual measurements to analyze power consumption of variable wordlength. However, more rapid analysis and estimation done at gate-level and function-level are required for large scale circuits. We present a new power modeling approach where both voltage scaling and switching activities are modeled as DWVS parameters.

Item Type:Thesis (PhD)
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
ID Code:2853
Deposited By:Normajihan Abd. Rahman
Deposited On:23 Nov 2012 20:36
Last Modified:23 Nov 2012 20:36

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