Efficient architectures for 3D HWT using dynamic partial reconfiguration

Ahmad , Afandi and Krill, Benjamin and Amira, Abbes and Rabah, Hassan (2010) Efficient architectures for 3D HWT using dynamic partial reconfiguration. Journal of Systems Architecture: the EUROMICRO, 56 (8). pp. 305-316. ISSN 1383-7621

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Official URL: http://dx.doi.org/10.1016/j.sysarc.2010.02.001

Abstract

This paper presents the design and implementation of three dimensional (3D) Haar wavelet transform (HWT) with transpose based computation and dynamic partial reconfiguration (DPR) mechanism on field programmable gate array (FPGA). Due to the separability property of the multi-dimensional HWT, the proposed architecture has been implemented using a cascade of three N-point one dimensional (1D) HWT and two transpose memories for a 3D volume of NxNxN suitable for real-time 3D medical imaging applications. These applications require continuous hardware servicing, hence DPR has been introduced. Two architectures were synthesised using VHDL and implemented on Xilinx Virtex-5 FPGAs. Experimental results and comparisons between different configurations using partial and non-partial reconfiguration processes and a detailed performance analysis of the area, power consumption and maximum frequency are analysed in this paper.

Item Type:Article
Uncontrolled Keywords:dynamic partial reconfiguration (DPR); haar wavelet transform (HWT); medical image processing
Subjects:T Technology > TA Engineering (General). Civil engineering (General) > TA174 Engineering design
Divisions:Faculty of Electrical and Electronic Engineering > Department of Computer Engineering
ID Code:3621
Deposited By:Normajihan Abd. Rahman
Deposited On:23 Jan 2017 15:05
Last Modified:23 Jan 2017 15:05

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