FPGA-assisted assertion-based verification platform

Mohamad, Nurita and Chia, Yee Ooi and Jwing Teh, Jwing Teh and Paraman, Norlina and Hassan, Hasliza and Ismail, Nordinah (2020) FPGA-assisted assertion-based verification platform. Journal of Telecommunication, Electronic and Computer Engineering, 12 (1). pp. 15-24. ISSN 2289-8131

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Abstract

In this paper, field programmable gate array (FPGA)-assisted verification platform is devised to enhance the assertion-based verification methodology to address the issues of high demand of integrated circuit with the advanced features to be delivered to market within tight Time-To-Market. The concept of SystemVerilog Assertion (SVA) checker generator is introduced to translate non-synthesizable verification coding into hardware so-called assertion checker in Verilog. A lookup table, which comprises of SVA operators mapped to their corresponding synthesizable Verilog coding was developed to generate assertion checker, which produces a single bit 1 when the assertion fails. Collection module implemented using a memory block and an arbiter was devised to be simple and fast enough to collect assertion results from the assertion checker. Since assertion checker can produce assertion result at any time, an arbiter is required to act as an interface between assertion checker and collection module. Case studies have been conducted on the proof-of-concept designs, which are the first�in-first-out (FIFO), up-down counter and Context Adaptive Variable Length Coding (CAVLC) to evaluate the effectiveness of the proposed FPGA-assisted verification platform. In the case studies, we have shown that the proposed FPGA-assisted verification platform works correctly. Besides, we also evaluated the method in area utilizations (ALMs). It has been proven that simulation-based verification time can be reduced for as much as 50% for complexity of VLSI design. Thus, implementing assertions using hardware such as FPGA becomes a solution to alleviate issue of long simulation time.

Item Type:	Article
Uncontrolled Keywords:	Arbitration; assertion-based verification; assertion checker; FPGA; system verilog assertion; verilog.
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics > TK7885-7895 Computer engineering. Computer hardware
Divisions:	Faculty of Electrical and Electronic Engineering > Department of Electronic Enngineering
Depositing User:	Mr. Abdul Rahim Mat Radzuan
Date Deposited:	10 Mar 2022 03:33
Last Modified:	10 Mar 2022 03:33
URI:	http://eprints.uthm.edu.my/id/eprint/6620

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