An optimized algorithm for simultaneous routing and buffer insertion in multi-terminal nets

Eh Kan, Chessda Uttraphan and Shaikh-Husin, N. (2015) An optimized algorithm for simultaneous routing and buffer insertion in multi-terminal nets. In: International Conference on Electrical and Electronic Engineering 2015 (IC3E 2015), 10-11 August 2015 , Melaka, Malaysia.

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Abstract

In today’s VLSI design, one of the most critical performance metric is the interconnect delay. As design dimension shrinks, the interconnect delay becomes the dominant factor for overall signal delay. Buffer insertion is proven to be an effective technique to minimize the interconnect delay. In conventional buffer insertion algorithms, the buffers are inserted on the fixed routing paths. However, in a modern design, there are macro blocks that prohibit any buffer insertion in their area. Many conventional buffer insertion algorithms do not consider these obstacles. This paper presents an algorithm for simultaneous routing and buffer insertion using look-ahead optimization technique. Simulation results show that the proposed algorithm can produce up to 47% better solution compared to the conventional algorithms. Although research has shown that simultaneous routing and buffer insertion is NP-complete, however, with the aid of look-ahead technique, the runtime of the algorithm can be reduced significantly.

Item Type:Conference or Workshop Item (Paper)
Uncontrolled Keywords:buffer insertion; VLSI routing; VLSI design automation; dynamic programming
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
Divisions:Faculty of Electrical and Electronic Engineering > Department of Computer Engineering
ID Code:7173
Deposited By:Normajihan Abd. Rahman
Deposited On:28 Oct 2015 11:28
Last Modified:28 Oct 2015 11:28

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