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Gate length effect on nmos electrical characteristics using tcad tools.

Osman , Kahar and Sanudin, Rahmat (2008) Gate length effect on nmos electrical characteristics using tcad tools. In: Engineering Postgraduate Conference (EPC), Bangi, Selangor.


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The concept of device scaling in silicon transistor has consistently resulted in better device density and performance. In conventional MOSFETs, control of Ioff for scaled devices requires very thin gate dielectrics and high doping concentrations. The industry roadmap for CMOS technology predicts physical limitations as well as practical technological will become barriers to continuous scaling. As the downscale of CMOS technology approaches physical limitations, the need arises for alternative device structures. NMOS traditionally has been the dominant MOS technology. Relative to CMOS, NMOS shows higher speed, higher-power technology with lower cost and higher functional density.

Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: silicon transistor; NMOS; gate length
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Faculty of Electrical and Electronic Engineering > Department of Electronic Engineering
Depositing User: Mrs Hasliza Hamdan
Date Deposited: 29 Mar 2012 04:28
Last Modified: 29 Mar 2012 04:28
URI: http://eprints.uthm.edu.my/id/eprint/2293
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