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Simulation study on NMOS gate length variation using TCAD Tool

Sanudin, Rahmat and Sulong, Muhammad Suhaimi and Morsin, Marlia and Abd Wahab, Mohd Helmy Simulation study on NMOS gate length variation using TCAD Tool. Compilation of Papers - VOLUME 1.


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The process of scaling in silicon transistor has consistently resulted in smaller device geometry, higher device density and better performance. In conventional MOSFETs, control of loff for scaled devices requires very thin gate dielectrics and high doping concentrations. The industry roadmap predicts the barriers of continuous scaling will be due to physical limitations as well as practical technology. As the downscale of CMOS technology approaches physical limitations, the need arises for alternative device structures. Thus, this paper intends to study the effect of various gate lengths on the NMOS electrical characteristic by means of simulation study.

Item Type: Article
Subjects: T Technology > T Technology (General)
Divisions: Faculty of Electrical and Electronic Engineering > Department of Electrical Technology
Depositing User: Normajihan Abd. Rahman
Date Deposited: 31 May 2012 06:58
Last Modified: 31 May 2012 06:58
URI: http://eprints.uthm.edu.my/id/eprint/2478
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