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IDD scan test method for fault localization technique on CMOS VLSI failure analysis

Abdullah, Farisal and Nayan, Nafarizal and Abdul Jamil , Muhammad Mahadi and Kamsin, Norfauzi IDD scan test method for fault localization technique on CMOS VLSI failure analysis. In: International Conference on Software Engineering (ISCE2010), 28-30 June 2010, Melaka, Malaysia .

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Abstract

One of the fashionable stress test has been practice on CMOS VLSI recently known as IDDQ scan test. It have competency to be as a part of failure analysis method in localization latent defect with nano scale geometry, i.e. gate oxide hole. An extension study in this field delivers proficiency on logic circuit diagnostic. From the result obtained during experiment, shown that the IDD scan test can be applied efficiency in triggering significant emission spot during anomalous logic transition.

Item Type: Conference or Workshop Item (Paper)
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
Divisions: Faculty of Electrical and Electronic Engineering > Department of Electronic Engineering
Depositing User: Normajihan Abd. Rahman
Date Deposited: 13 Feb 2013 08:09
Last Modified: 21 Jan 2015 08:09
URI: http://eprints.uthm.edu.my/id/eprint/3017
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