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ASIC design methodologies for 3D NoC-based 3D heterogenous MPSoC

Jabbar, Mohamad Hairol (2013) ASIC design methodologies for 3D NoC-based 3D heterogenous MPSoC. PhD thesis, Universite de Grenoble.

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Abstract

For many years, Moore's Law has been the primary driving force enabling the evolution of semiconductor industry with the ability to double the transistor count on a silicon die for every two years. However, shrinking transistor dimensions, also known as CMOS scaling to be able to design and manufacture higher performance devices has become much more difficult than it is previously as we are approaching very deep submicron technologies such as 20 nm and beyond. The issues of design complexity and the exponential increase of cost to manufacture devices based on these very deep submicron technologies are among the great hurdles currently being faced by the industry making it unattractive performance per cost solution. The transition to 450 mm (18") wafer to help reducing manufacturing cost for advanced process technology and the development of extreme ultraviolet (EUV) lithography tools are also facing technical difficulties that remain to be solved in the next several years while at the same time requires multi billion dollar investment to build new manufacturing facilities as well as new processing equipments. 3D integration has been around since decades ago but only now the industry is paying great attention to this technology as a result of economical and technical difficulties that arise from the / transistor shrinking in 2D technology. It has been the,subject of' extensive research in the industry and academia due to benefits it could potentially offer such as higher performance, lower power consumption, larger memory bandwidth, small form factor and support for heterogeneous technology integration making it suitable for several application domains particularly in mobile devices. 3D technology could provide higher memory bandwidth through its excessive vertical connections using TSV or microbumps as in wide I/0 memory architecture and can also accomodate high memory capacity when using memory-on-logic or memory-on-memory stacking. Shorter vertical interconnection between stacked dies or wafers as well as reduction of horizontal wirelength due to stacking will eventually provide higher performance per watt. However, there are also some challenges that exist in 3D technology and they have to be solved before it can be widely adopted as a mainstream technology for high volume production such as high temperature effect, testing of 3D architecture and most importantly for the designers is 3D design tools, specifically the tools that are capable of doing 3D synthesis, 3D place and route as well as 3D optimization at each step. With the recent trend of mainstream multipr~cessort echnology that is moving towards increasing the number of processing cores to support higher performance applications, Network-on-Chip (NoC) has become the primary technology in meeting the demand of high performance, scalability v and flexibility for processor's and Intellectual Property (IP) cores' communication. Works on multiproce~sor and NoC architecture in 3D technology have been carried out for many years covering various issues such as partitioning method and NoC topologies but most of the prior works only consider software simulation for the performance analysis where the results is less accurate and therefore cannot be truly used for evaluating the benefits bring by 3D technology. The need for performance analysis from design implementation results is highly desirable to be able to make the right conclusions regarding the potential benefits it offers. In this thesis, we study the 3D NoC architectures through physical design implementations using real 3D technology being implemented in the industry. Based on the routed netlists, we conduct performance analysis to evaluate the 4 :? '. benefit of 3D architecture compared with its 2D implementation. But firstly, we present ou$ initial work designing and implementing a 2D NoC-based MPSoC architecture on FPGA intended to identify design issues related to the 2D MPSoC design. Based on the proposed 3D design flow focusing on timing verification by leveraging the benefit of negligible delay of microbumps structure for vertical connections, we have conducted partitioning techniques for 3D NoC-based MPSoC architecture including homogeneous and heterogeneous stacking using Tezzaron 3D IC technlogy. Design and implementation trade-off in both partitioning methods is investigated to have better insight about 3D architecture so that it can be exploited for optimal performance. Using homogeneous 3D stacking approach, NoC architectures are explored to identify the best topology between 2D and 3D topology for 3D MPSoC implementation. The architectural explorations have also considered different process technologies highlighting the wire delay effect to the 3D architecture performance especially for interconnect-dominated design. Additionally, we performed heterogeneous 3D stacking of NoC-based MPSoC implementation with GALS style approach and presented several physical designs related analyses regarding 3D MPSoC design and implementation using 2D EDA tools. - Finally we conducted an exploration of 2D EDA tool on different 3D architecture to evaluate the impact of 2D EDA tools on the 3D architecture performance. Since there is no commercialize 3D design tool until now, the experiment is important on the basis that designing 3D architecture using 2D EDA tools does not have a strong and direct impact to the 3D architecture performance mainly because the tools is dedicated for 2D architecture design. Integrating manual tools (scripts to constraint the design) to the 2D EDA tools to design 3D architecture is the common method to achieve performance benefit but this method loses the most important design step of 3D optimization that normally exists in the 2D EDA tools when designing 2D architecture.

Item Type: Thesis (PhD)
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
Depositing User: Normajihan Abd. Rahman
Date Deposited: 29 Jun 2015 06:43
Last Modified: 29 Jun 2015 06:43
URI: http://eprints.uthm.edu.my/id/eprint/4665
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