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FPGA prototyping of universal asynchronous receiver-transmitter (UART) using altera VHDL implementation

Ahmad, Nabihah@Nornabihah (2005) FPGA prototyping of universal asynchronous receiver-transmitter (UART) using altera VHDL implementation. Masters thesis, Kolej Universiti Teknologi Tun Hussein Onn.

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Abstract

External devices such as modems and other computers need to communicate serially. In order to provide this communication, a universal asynchronous receivertransmitter (UARn can provide an asynchronous serial data communication with I/O outputs devices such as keyboard, mouse or keypad. It can transmit serial data on over it's transmit line (TxD) and receive serial data over it's receive line (RxD). This project describes a universal asynchronous receiver-transmitter (UART) design. It is design from Very High Speed Integrated Circuit Hardware Description Language (VHDL) description, and then to Field Programmable Gate Array (FPGA) implementation. VHDL is used to provide a simple way of design entry through behavioral description. This project covers VHDL integration issue involved in the flow from high-level description to a fully simulated and synthesized. FPGA University Program Educational Board (UP2) is used to achieve fast prototype build and logic circuit verification. Then analysis the features of other existing UART technology design.

Item Type: Thesis (Masters)
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
Depositing User: M.Iqbal Zainal A
Date Deposited: 19 Apr 2011 03:17
Last Modified: 14 Jan 2020 03:50
URI: http://eprints.uthm.edu.my/id/eprint/932
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