4-bits 0.25 μm CMOS low power flash ADC

Abbas Al-Sahlanee, Rayed Awad (2015) 4-bits 0.25 μm CMOS low power flash ADC. Masters thesis, Universiti Tun Hussein Onn Malaysia.

[img]
Preview
PDF
797Kb

Abstract

The analogue to digital converters are the key components in modern electronic systems. Signal processing is very important in many of the system on-a-chip applications. Analogue to digital converters (ADCs) are a mixed signal device that converts analogue signals which are real world signals to digital signals for processing the information. As the digital signal processing industry grows the ADC design with new techniques and methods are extensively sought after. This increases the requirements on ADC design concerning for high speed, low power and small area. A flash ADC is the best solution, not only for its fast data conversion rate but also it becomes part of other types of ADC. However main problem with a flash ADC is its power consumption, which increases in number of bits. In this project a 4-bits flash ADC is designed with a 1.5V power supply and 1.5 GHz clock using 0.25 μm CMOS technology. The software used for this ADC design is Tanner EDA’s S-EditTM and T-SpiceTM which is utilized to simulate the three blocks of flash ADC with input frequency of 250 MHz. The ADC is successfully designed with a power consumption of 5.18 mW.

Item Type:Thesis (Masters)
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
ID Code:7566
Deposited By:Normajihan Abd. Rahman
Deposited On:02 Mar 2016 09:27
Last Modified:02 Mar 2016 09:27

Repository Staff Only: item control page