New architecture of low area AES S-Box/Inv S-Box using VLSI implementation

Ahmad, Nabihah@Nornabihah (2016) New architecture of low area AES S-Box/Inv S-Box using VLSI implementation. Jurnal Teknologi (Sciences & Engineering), 78 (5–9). pp. 21-25. ISSN 21803722

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Abstract

The Substitution box (S-box) is one of the core of Advanced Encryption System (AES) implementation and the only non-linear transformation. It is consumed most of the power in AES hardware. This paper present a low-complexity design methodology for the S-box/ InvS-box which includes minimising the comprehensive circuit size and critical path delay, scaling down the transistor size, along with selecting an advanced technology for an optimised CMOS full custom design. The area of the circuit is about 39.44 μm2, while the hardware cost of the S-box/InvS-box is about 147 logic gates, with a critical path propagation delay of 3.235ns.

Item Type:Article
Uncontrolled Keywords:AES; s-box/invs-box; VLSI; low area
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
Divisions:Faculty of Electrical and Electronic Engineering > Department of Electronic Engineering
ID Code:8553
Deposited By:Mr. Mohammad Shaifulrip Ithnin
Deposited On:03 Jul 2017 08:54
Last Modified:03 Jul 2017 08:54

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